Silicon-On-Insulator (SOI) technology has been investigated for SRAM chips for several years. Advantages of the technology include simplified layout, avoidance of latch-up, reduced leakage currents and junction capacitances, and thus faster speeds and lower power consumption. For memories, the reduction of the junction capacitance lowers the bitline capacitance, which is a major limiting factor in memory performance.
SOI for SRAMs has been investigated in both fully-depleted and partially-depleted processes. The fully-depleted process is more difficult to perform but has certain desired circuit behaviors, including less history dependence and less parasitic bipolar currents. A fully-depleted device has an ultrathin silicon film used such that the depletion layer extends through the entirety of the film, eliminating the floating-body effect and providing superior short-channel behavior.